In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.

The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

Figure 1: Capacitance Multiplier

The voltage follower functions to isolate the capacitance created by the circuit from the loading incurred by the inverting amplifier. Since no current enters the op amp's input terminals, the feedback capacitor carries the input current.

By applying Kirchhoff's Current Law (KCL), a relation between input and output voltage with respect to resistances can be established, which can be further substituted into the current expression. Rearranging the expressions aids in determining the input impedance. By selecting appropriate resistance values, an effective capacitance can be generated between the input terminal and ground that is a multiple of the physical capacitance.

To prevent op-amps from saturating, the effective capacitance must be limited by the inverted output voltage. As the capacitance multiplication increases, the maximum allowable input voltage must decrease. Capacitance multiplier circuits such as this one provide an efficient solution for generating larger capacitances without increasing the physical capacitance.