Name: fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology
Uploaded: 2015-12-07T13:00:00.000+00:00
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Description: Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

Atenção: Por favor, consulte todas as fichas de dados de segurança do material (MSDS) relevantes antes de usar. Vários dos produtos químicos utilizados no presente processo de fabricação são altamente tóxicos e cancerígenos. Os nanomateriais podem ter riscos adicionais em comparação com o seu homólogo granel. Utilize todas as práticas de segurança adequadas quando trabalhar com equipamentos, produtos químicos ou nanomateriais, incluindo o uso de controles de engenharia (extractor de fumo) e equipamentos de proteção individual (óculos de segurança, luvas, roupas de sala limpa). 1. Alinhamento marcador de definição para Litografia <ol><li> Comece com grau industrial polido single-sided Si (100) bolachas com qualquer n ou p-type doping. </li><li> Revestir a bolacha com 1,4 uM de fotorresistente positivo. Executar uma 90 seg hexametildissilazano (HMDS) de tratamento a 130 ° C para promover a adesão do foto-resistente, seguido de arrefecimento da bolacha em uma placa fria, spin-coating à velocidade apropriada (3.500 rpm), e um 90 seg coza macio umt 95 ° C. </li><li> O uso da máscara foto-litografia e uma ferramenta de exposição expor as marcas de alinhamento, dose de exposição de 120 mJ / cm 2. </li><li> Realize um único processo de desenvolvimento poça. Executar um 90 seg 115 ° C coza pós-exposição, seguido por 60 sec desenvolvimento utilizando desenvolvedor e asse dura 90 seg a 100 ° C para curar a resistir. </li><li> Usar um microscópio para inspeccionar se as aberturas na parte de resistir são as dimensões correctas. </li><li> Etch 120 nm de Si usando corrosão por plasma de cloro. Esta espessura confere um bom contraste para os sistemas de alinhamento automático da ferramenta de exposição utilizado neste trabalho. Por exemplo, utilizando um plasma indutivo acoplado (ICP): 20/40 sccm de O2 / CF 4, 5 mTorr, 60/500 W cilindro / potência de RF ICP, 10 seg avanço óxido de decapagem, seguido por 80/40 sccm Cl 2 / HBr , 60 mTorr, 20/500 W placa / potência ICP RF, 35 seg Si gravar. </li><li> Use um descascador de plasma de oxigênio para remover o fotorresiste (1 kW, 400 sccm O 2 com endpodetecção int e 2 min overetch). À medida que o revestimento fotoprotector é curado pelo solvente como acetona plasma normal não pode ser utilizado. </li><li> Limpe as bolachas. Primeiro colocá-los durante 10 min em 99% HNO 3, seguido de enxaguamento com água desionizada até que a resistividade da água é de 5 mohms (limpo orgânico). Após este limpa as bolachas durante 10 min em HNO3 65% a 110 ° C, seguido de enxaguamento com água desionizada até que a resistividade da água é de 5 mohms (metal limpo). Use um secador para secar rinser as bolachas. </li></ol> 2. metal inferior e Interlayer dielétrica Deposição <ol><li> Use pulverização por magnetrão a depositar a camada de metal da parte inferior através do teste. Uma pilha de três camadas metálicas tem de ser depositado: 500 nm de Ti, de 50 nm de TiN, Ti e 100 nm. A primeira camada de Ti é reduzir a resistência da pilha, a lata é a camada de suporte para o crescimento efectivo CNT, e o topo Ti é para proteger o TiN contra danos plasma quando condicionamento da camada de SiO2 12 </sup&gt;. Realizar Ti pulverização catódica utilizando um alvo de Ti puro com Ar-plasma a uma temperatura de substrato de 350 ° C. De estanho na forma de pulverização catódica reactiva usar uma combinação de Ar e n 2, de novo, a 350 ° C temperatura do substrato. </li><li> Usando deposição de vapor químico melhorado por plasma (PECVD), depositar um 1 um espessa camada de SiO2. Aqui ortossilicato de tetraetilo (TEOS) é usado como precursor a uma temperatura de cilindro de 350 ° C. <ol><li> Verifique a espessura da camada de SiO 2, utilizando uma ferramenta adequada, por exemplo um reflectómetro ou elipsometria. </li></ol></li><li> Revestir a bolacha com 1,4 uM de fotorresistente positiva, começando com um tratamento de 90 seg HMDS a 130 ° C, seguido de arrefecimento da bolacha em uma placa fria, spin-coating à velocidade apropriada (3.500 rpm), e um 90 seg suave cozer a 95 ° C. </li><li> O uso da máscara foto-litografia e uma ferramenta de exposição, expor o padrão desejado de aberturas, que será mais tarde a gravadas em SiO2 to formar as vias, alinhados com os marcadores de alinhamento, dose de exposição de 140 mJ / cm 2. </li><li> Realizar um único processo de desenvolvimento de uma poça de partida com 90 seg 115 ° C de pós-exposição assar, seguido por 60 seg desenvolvimento utilizando revelador e coze dura 90 segundos a 100 ° C. </li><li> Usar um microscópio para inspeccionar se as aberturas na parte de resistir são as dimensões correctas e se a sobreposição para os marcadores de alinhamento está correcto. </li><li> Plasma gravar as aberturas de contacto no SiO 2. Por exemplo, usar um etcher plasma triodo com C 2 F 6 / CHF 3 36/144 sccm a 180 mTorr e 300 W de potência de RF. Se necessário, efectuar testes de taxa de corrosão sobre uma bolacha de teste, a fim de minimizar mais de gravura a 5% -10% no tempo. Nota: Embora o Ti é resistente ao ataque químico reactivo neste flúor química, a exposição prolongada ao plasma resultará na corrosão física da camada de Ti. Se a camada de estanho é exposta ao plasma isso terá um influenzae negativoce sobre o crescimento da CNT 12. Não use condicionamento úmido, pois isso irá resultar em muito alargamento das aberturas, tornando o top de metalização na parte 4 problemático. </li><li> Retirar a camada de Ti sacrificial por ataque úmido em 0,55% HF durante 60 segundos. Depois de gravar lavar as bolachas com água DI até a resistividade da água é de 5 mohms e usar um secador para secar rinser as bolachas. Nota: Usando um microscópio pode ser verificado se a camada de Ti está gravado, a camada de estanho terá uma cor marrom-ouro, enquanto o Ti é cinza metálico. </li></ol> 3. Catalisador Deposição e Crescimento CNT <ol><li> Evapora-se 5 nM de Co utilizando um evaporador e-beam. Bombear para baixo até pelo menos 2x10 -6 Torr, e aquecer as bolachas a 60 ° C, utilizando lâmpadas sob vácuo antes de depositar para remover qualquer película de água. A foto-resiste usado para definir as aberturas de contato é mantido na bolacha de proporcionar auto-alinhamento do catalisador para as aberturas de contacto no SiO 2. </li><li> Removero Co fora das aberturas de contacto por lift-off. Para a co, verificou-se que o tetra-hidrofurano (THF) dá os melhores resultados de lift-off e crescimento a baixas temperaturas. N-metil-2-pirrolidona (NMP), que foi previamente utilizado para a descolagem Fe após evaporação, foi encontrada a danos Co demasiado tal forma a impedir qualquer crescimento CNT alinhados. Coloque a bolacha durante 15 minutos num banho de ultrassons com THF a 35 ° C. Lavar com água desionizada, durante 5 min e secar utilizando uma pistola de Spinner ou azoto. </li><li> Inspecione o wafer debaixo de um microscópio e verificar se há resíduos de resistir. Se os resíduos permanecem realizar um tratamento mais ultra-som em THF, e, opcionalmente, use um cotonete macio especial para fins de lift-off para limpar manualmente longe resíduos. </li><li> Execute o crescimento CNT usando deposição de vapor químico de baixa pressão (LPCVD). Utilize a seguinte receita: 8 min de pré-recozimento a 350 ° C com 700 sccm de H 2 a 80 mbar, seguido de crescimento CNT por adição de 50 sccm C 2 H 2. A 350 ° C, 60min de crescimento dá cerca de 1 uM de CNT. Se for necessário efectuar um teste de crescimento para ajustar a altura, que devem ser da mesma espessura que a camada de SiO2. Resfriar o reator e limpar usando N2. </li><li> Use um microscópio eletrônico de varredura para verificar a altura do CNT no interior das aberturas sob 45 ° de inclinação, ou através da preparação de uma secção transversal. </li><li> Inspeccionar as amostras utilizando espectroscopia de Raman para determinar a cristalinidade do CNT 18. </li></ol> 4. Topside Metalização <ol><li> Use pulverização catódica para depositar o topo metal. Como Ti é um bom metal para o contactar CNT 19, primeiro por pulverização catódica 100 nm de Ti, seguido por 2 mm de Al (1% Si) sem quebrar o vácuo. </li><li> Revestir a bolacha com 3,1 uM de fotorresistente positiva com viscosidade mais elevada, a partir de um tratamento de 90 seg HMDS a 130 ° C, seguido de arrefecimento da bolacha em uma placa fria, spin-coating a 3.000 rpm, e um cozimento macio 90 seg a 95° C. </li><li> O uso da máscara foto-litografia e uma ferramenta de exposição expor o padrão de metal superior alinhada com as marcas de alinhamento, dose de exposição de 420 mJ / cm 2, o foco de -1. </li><li> Realize um único processo de desenvolvimento poça. Isso começa com um 90 seg 115 ° C pós-exposição de bolos, seguido por 60 sec desenvolvimento utilizando desenvolvedor e asse dura 90 seg a 100 ° C. </li><li> Usar um microscópio para inspeccionar se as linhas no resistir são das dimensões correctas e se a sobreposição para os marcadores é correcta. </li><li> Etch a pilha de Ti / Al utilizar gravação por plasma de cloro. Por exemplo, utilizando um plasma indutivo: 30/40 sccm Cl 2 / HBr, 5 mTorr, 40/500 poder W Platen / ICP RF com detecção de endpoint e 80% overetch usando 15/30 sccm Cl 2 / HBr. </li><li> Use um descascador de plasma de oxigênio para remover o fotorresiste (1 kW, 400 sccm O 2 com a detecção de endpoint e 2 min overetch). Se a cobertura não é completa de metal (isto é, existem orifícios em torno daCNT) usar um solvente orgânico (por exemplo, NMP) para remover o material fotosensitivo, a fim de evitar danos no plasma para o CNT. </li><li> Limpe as bolachas. Colocá-los durante 10 min em 99% HNO 3, seguido de enxaguamento com água desionizada até que a resistividade da água é de 5 mohms (limpo orgânico). Use um secador para secar rinser as bolachas. </li></ol> 5. Medições <ol><li> Use um microscópio eletrônico de varredura de acordo com as instruções do fabricante para verificar o top metalização das bolachas. Nota:. Como as amostras são electricamente condutora ter para ser usado sem passos de tratamento adicionais, se necessário, a bolacha pode ser clivado mecanicamente, a fim de verificar o CNT completa através de usar uma inclinação amostra de 90 °, resultando em imagens, como mostrado na Figura 3 e as amostras podem ser directamente montado no SEM. Geralmente, tensões de aceleração de 15 kV ou 20 pode ser utilizado, mas, se a camada de SiO2 está a carregar-se demasiado este pode ser reduzido tO 5 kV. </li><li> Efectuar as medições de 4 pontos sonda IV, utilizando uma estação sonda, em combinação com um parâmetro analisador semicondutor, tal como descrito na Figura 1 e na Vollebregt et ai. 16. Nota: Normalmente uma varredura tensão de -0,5 a 0,5 V é suficiente, como a queda de potencial através de uma interligação ideal é pequena. Ao usar uma configuração de sonda de 4 pontos a resistência de contato das agulhas da sonda e as resistências de fio da configuração são omitidos. </li></ol>

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The authors have nothing to disclose.

A Figura 1 mostra uma vista geral esquemática da estrutura fabricada neste trabalho, e que foi utilizado para as medições de sonda de 4 pontos. À medida que o potencial é medido por meio de sondas que transportam nenhuma corrente, a queda de potencial exacto (VH-VL) através do feixe CNT central e os contactos para o metal pode ser medido. Maior diâmetro feixes CNT são usadas para contactar a camada de estanho inferior das almofadas de contacto, a fim de reduzir a resistência total pa...

Cobre e tungstênio, os metais que são actualmente utilizados para as interconexões em tecnologia state-of-the-art de muito grande escala de integração (VLSI), estão se aproximando de seus limites físicos em termos de confiabilidade e condutividade elétrica 1. Enquanto transistores down-dimensionamento geralmente melhora seu desempenho, ele realmente aumenta a resistência ea densidade de corrente das interconexões. Isto resultou em interconexões dominando o desempenho do circuito integrado (IC) em termos de atraso e consumo de energia 2. Os nanotubos de carbono (CNT) têm sido sugeridos como alternativa para o Cu e W metalização, especialmente para interconexões verticais (vias) como facilmente pode CNT sido cultivadas verticais 3. CNT tenha sido demonstrado que possuem uma excelente fiabilidade eléctrica, permitindo um até 1000 vezes mais elevada do que a densidade de corrente de Cu 4. Além disso, a CNT não sofrem de superfície e contorno de grão de dispersão, que está a aumentar o resistivity de Cu em escala nanométrica 5. Finalmente, CNT foram mostrados para ser excelentes condutores térmicos 6, que podem ajudar no tratamento térmico em chips VLSI. Para a integração bem sucedida da tecnologia CNT em VLSI, é importante que os processos de crescimento para o CNT é tornado compatível com o fabrico de semicondutores. Isto exige que o baixo crescimento da temperatura do CNT (&lt;400 ° C), utilizando materiais e equipamentos que são considerados compatíveis e escalável para a fabricação em grande escala. Embora muitos exemplos de vias de teste CNT tem sido demonstrado na literatura 7,8,9,10,11,12,13,14, a maioria destes Fe utilizar como catalisador o que é considerado como um contaminante no fabrico de IC 15. Além disso, a temperatura de crescimento utilizados em muitos destes trabalhos é muito maior do que o limite superior de 400 ° C. Preferencialmente CNT deve ainda ser cultivadas abaixo de 350 ° C, a fim de permitir a integração com baixo-k dieléctricos modernos ou flexívelsubstratos. Aqui é apresentado um método para o cultivo de escalável CNT a temperaturas tão baixas como 350 ° C, utilizando como catalisador Co 16. Este método é de interesse para a fabricação de diferentes estruturas eléctricas que consistem em alinhados verticalmente CNT em circuitos integrados, variando de interconexão e eletrodos para capacitores super e dispositivos de emissão de campo. O catalisador de metal de Co é muitas vezes usado no fabrico de circuitos integrados para a fabricação de silicieto de 17, enquanto o estanho é um material de barreira usado muitas vezes 7. Além disso, nós demonstramos um processo para a fabricação de vias de teste CNT enquanto apenas utilizando técnicas de fabricação de semicondutores padrão. Com isso, vias de teste CNT são fabricados, inspecionado por microscopia eletrônica de varredura (MEV) e espectroscopia Raman, e eletricamente caracterizada.

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

O design da estrutura de medição utilizado neste trabalho podem ser encontrados na Figura 1. Empregando uma tal estrutura a medição da resistência feixe CNT e as resistências de contacto de metal-CNT pode ser determinada com precisão, como sonda e resistências de arame são contornadas. A resistência do pacote é uma medida para a qualidade e densidade do pacote CNT. A fim de determinar os feixes de resistência de contacto de comprimentos diferentes devem ser medidos. <p c...

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Fabricação de Baixa Temperatura de Nanotubos de Carbono Vertical Interconexões Compatível com Semiconductor Tecnologia

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Universidad de Cartagena UDEC

Research

JoVE Journal

Engineering

7.6K visualizações.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

Vídeo: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

Fabricação, Densificação e Replica Moldagem de Microestruturas de Nanotubos de Carbono 3D

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

Engenharia

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

Confecção Nanogaps por Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Química

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

Oxidação seca e vácuo Annealing Tratamentos para Ajustando as propriedades de umectação Matrizes Nanotubos de Carbono

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

Ultra Density Array of alinhados verticalmente Nanofios orgânicos pequeno-moleculares sobre substratos Arbitrárias

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

Fabricação de tridimensionalmente microestruturadas nanocompósitos através Microfluidic Infiltração

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Fabricação de cavidades de nanoescala uniformes via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

Fabricação de Nanotubos de Carbono de Alta Frequência Nanoelectronic Biosensor de Sensoriamento em High Solutions força iônica

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengenharia

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Dieletroforese assistida por fluxo: Um método de baixo custo para a fabricação de dispositivos de solução-processable nanofio de alto desempenho

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Um método padrão e confiável para fabricar nanoelectrónica bidimensional

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.